[Solved] Maths + 4ms shuffling clock multiplier (SCM) confusion

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tdallas
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[Solved] Maths + 4ms shuffling clock multiplier (SCM) confusion

Post by tdallas » Mon Apr 05, 2021 6:21 am

Hi. Maybe somebody can help a confused wiggler. I have build a 4ms SCM which works fine in general.

But when I use one of the two cycling channels on Maths to send trigger/gates to the SCM inputs the affected channel on Maths goes high and stay there until I pull the cable.

The strange thing is: this doesn’t happen when I use the EOR / EOG or the attenuverted output 1 / 4 on Maths. It also doesn’t happen when I send the Maths channel to one of the attenuverted ones first (lets say right channel -> channel 3 -> SCM) or through a buffered mult. No other tested module behave like this when talking to the SCM yet.

What could this be? :hmm:

Edit: might this be a protection for the gate/trigger inputs on the SCM? Because this also happens on the expander (Resync, 4xFast, Mute). The other CV inputs there works fine with Maths.
Last edited by tdallas on Mon Apr 12, 2021 3:34 pm, edited 6 times in total.

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Re: Maths + 4ms shuffling clock multiplier (SCM) confusion

Post by tdallas » Mon Apr 05, 2021 7:25 am

Maybe a kind wiggler with a Maths and a factory or DIY build SCM could try this? Is the “always high” state a normal behavior on the both main Maths channels if connected to the SCM gate/trigger inputs?

Thanks a lot in advance!

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Re: Maths + 4ms shuffling clock multiplier (SCM) confusion

Post by tdallas » Wed Apr 07, 2021 12:37 pm

Ok. Since this “always high” behavior on Maths also happens with the CV inputs on my two passive Meng Qi DPLPG I would assume that this is somehow related to the main outputs of Maths channel 1 + 4 (unbuffered? / impedance?) ... in the moment one is going through a buffered mult or using the attenuated outs on Maths it works like a charm on both DPLPG and SCM. Very strange, but why not
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Re: Maths + 4ms shuffling clock multiplier (SCM) confusion

Post by tdallas » Mon Apr 12, 2021 3:33 pm

Final update on this topic in case somebody else might experience this behavior. Here is the explanation from Make Noise. Also a very big thanks to 4ms (Zach) for the help!

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The behavior that you have captured is known to occur when patching the Unity outputs to the inputs of these two particular modules [Meng Qi DPLPG, 4ms SCM DIY(not factory!)]. This occurs because of an impedance mismatch between the modules' inputs and the Unity outputs.

The Unity outputs were designed to have low impedance so that a 1V/Octave CV could be patched to the Signal input, and if the CV was not slewed, the CV tracking would be unaffected by the module.

If a modules input is not buffered or if the input impedance is not appropriate for this type of signal, then the Unity output will lock up [...]

To patch the Unity output to one of these modules inputs, you will need to first patch the output signal to a buffered mult or to CH.2 or CH.3 of MATHS

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Re: [Solved] Maths + 4ms shuffling clock multiplier (SCM) confusion

Post by Oblivion » Mon Apr 12, 2021 3:48 pm

Thanks for the follow-up on this. I have DIY SCM and a Maths and though I'd not ever seen this, hopefully I'll recognize it if I eventually do.
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tdallas
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Re: [Solved] Maths + 4ms shuffling clock multiplier (SCM) confusion

Post by tdallas » Mon Apr 12, 2021 3:58 pm

Hi. You have to plug the unity out (channel 1 or 4) from Maths for example to the gate input of the SCM module. In my case the following happens:



This also happens on the Meng Qi DPLPG:


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