Adding sync to OTA VCO?

[dogfaceaudio]

I'm trying to add a sync input for a LM13700 based VCO, basically I'm just using a FET to short the timing cap to ground. I grabbed the gate to trigger schematic from Ken Stone, but I'm not sure if this is the correct method of driving the FET. Is there a better method of getting a gate to trigger circuit to drive a FET? Thanks!

[guest]

the input impedance on the JFET is high enough that you probably dont need the opamp, but you would have to bias the circuit to -5V or so. if you keep the opamp, the inverting pin should get another resistor to ground, to set it at a couple of volts. the gate of the JFET should have a resistor to ground to limit the voltage swing, and R48 should be at least 10k to limit input current when the gate become forward biased (the gate can handle -25V on the negative swing, and 10mA on the forward swing, but its best not to get too near these numbers, as they are the breakage points. -5V should shut it off just fine, and 1uA would be way more than enough to turn it on).

[slow_riot]

I like to use a comparator with an open collector output to drive an FET. You don't even need to use one with an uncommitted open collector, an LM339 or equivalent with the output transistor collector hardwired to the negative rail is what you need to drive an NPN FET. Don't forget a series protection diode to prevent reverse biasing the FET, the output of the comparator can potentially fry the FET.

[dogfaceaudio]

I switched the opamp to an inverting stage, how does this revised schematic look?

[guest]

you want to use the opamp as a comparator, so no feedback required! get rid of R67 and short out R66. you will need to bias it up so it is off for no input signal. also, since its inverting, a negative going trigger will do the sync function.

[dogfaceaudio]

After a few PM's back and forth with guest, I arrived at the following schematic to convert gate/sync to trigger a FET for shorting out the LM13700 timing capacitor.

[davestrength]

PAIA 9720 is another LM13700 based VCO with a soft sync (i.e. pass through cap) implemented. Worth a look as another reference.

[julios]

Sorry to bring back an old topic but my question may follow this one

How would one add soft sync to a triangle VCO similar to the one above?

Thanks in advance!

[guest]

soft sync is typically applied to the comparator threshold, which is the second OTA in the schematic. coupling in to the +input with a small value capacitor (1nF) might do the trick.

[julios]

soft sync is typically applied to the comparator threshold, which is the second OTA in the schematic. coupling in to the +input with a small value capacitor (1nF) might do the trick.

Thanks! Do you mean simply "injecting" the sync signal via this 1nF cap the + input?
If i understand it correctly i could add a switch before the JFET and switch between hard and soft sync?

[guest]

looking at it again, i think it would be best to run a 10k resistor from the juncture that goes to the first OTA up to the +input. this will help decouple the two OTAs so the sync signal doesnt effect the frequency when it doesnt cross the threshold. then put your 1nF cap to the +input. and you will need to put the switch before the hard sync comparator, as you want the sync signal to not be a square wave (thats what makes it a hard sync).