CEM3340 hard sync / reset phase

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Flub
Learning to Wiggle
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Joined: Fri Mar 06, 2020 1:39 pm

CEM3340 hard sync / reset phase

Post by Flub » Fri Mar 06, 2020 1:46 pm

Hey there,
is there any possibility with the CEM3340/AS3340 to get the following SYNC behaviour?
Image
It would be great to avoid popping sounds when using very short attack times.
Using the hard sync configuration shown in Figure 5 of the CEM3340/AS3340 datasheet it is only possible to reset the triangle to the peak negative voltage which is GND at Pin 10 and -5V after offsetting and adjusting levels for a -5/+5 range.
Image

Is there any way to restart the wave from its middle like it is shown in the image above?
Or is there another way to avoid those popping sounds when using very short attacked envelope and a vca to control the cem3340s amplitude?
regards,
Flub

pjbulls
Learning to Wiggle
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Re: CEM3340 hard sync / reset phase

Post by pjbulls » Fri Mar 06, 2020 2:07 pm

It is possible to reset a triangle core oscillator to the center of the cycle, though I wouldn't know how to go about it in an IC. The reason why this is usually not done anyway is because the slope of the oscillation will be retained, so the voltage will continue to rise if it was rising, or fall if it was falling. Resetting to the top or the bottom of the cycle is consistent regardless of when the sync pulse hits (see also here).

Flub
Learning to Wiggle
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Joined: Fri Mar 06, 2020 1:39 pm

Re: CEM3340 hard sync / reset phase

Post by Flub » Fri Mar 06, 2020 2:17 pm

Thanks for the reply,
I think it is only important to have to start from the middle in the case you want to amplify it with very short attacked envelopes.
I just tried around and found out that It must be possible by somehow modifying Pin 11 of the CEM3340/AS3340
Image

How could i discharge or charge the Cap on pin 11 very fast to a certain voltage without affecting the capacitance.
I just tried shortcutting this pin to some different levels. it worked but there were many oscillations due to the extra capacitance of my hands or so i think.
What kind of schematic would suit here to keep the overall stability of the oscillator but to be able to set the voltage to a specific level using a 5V trigger pulse.

Somehow like this but instead of resetting it to ground rather resetting it to a voltage.
Image
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EDIT
As i am not an expert i dont know to to quickly shortly connect an analog voltage to a point I only have the idea of a buffered voltage follower and a 4066 as a switch which is connected to pin11. But there must be a more professional way think.
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EDIT
Is this chip the solution? https://www.mouser.de/datasheet/2/389/stg719-955827.pdf
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EDIT
I think here they are doing something similar on IC16:
http://www.muzines.co.uk/articles/the-s ... siser/2624
Image
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EDIT
I think they described they solution here: (the mean "bottom right hand" corner i think)
The synchronisation circuit appears in the bottom left hand corner of Figure 4. S8b is the pole of the FM & Sync Function switch that controls this circuit. When sync is off (in the 'Off' and 'FM' positions) pin 13 of IC17d is held low blocking the pulse wave from VCO1, the 'master' oscillator. When sync is selected, the pulse wave is inverted by the NAND gate and the falling edges are differentiated to give 10us wide negative pulses that turn TR15 on. TR16 and TR17 are FET's that provide a low resistance path from C34, the integrator capacitor of IC16, to the potential divider R215,RV29,RV30 when either gate is allowed to go high. Without sync selected, the FET's are held off by R212 via D29 and D30. With S8 in the 'Sync I' or 'FM + Sync I' position, the gate of TR17 is connected to -15V holding it off, but on each sync pulse R213 is allowed to turn on TR16, and C34 discharges to the voltage set by RV30. With Sync II selected TR16 is held off and TR17 discharges C34 to the voltage on the wiper of RV29. Hence at the end of each cycle of VCO1, VCO2's waveform is reset to one of two positions depending on which type of synchronisation is selected.

Flub
Learning to Wiggle
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Joined: Fri Mar 06, 2020 1:39 pm

Re: CEM3340 hard sync / reset phase

Post by Flub » Sun Mar 08, 2020 3:01 pm

Hey there I tried the whole day to implement that circuit but it does not work really good yet.
This is the schematic of how I tried it. I wanted to avoid that IC 17 (NAND Schmitt trigger) so I tried to invert and shift the signal with the BC547 and an
voltage follower. The circuit only works if I increase the capacitance of C1 to for example 2.7nF. But then the pulse is much too long.
Can anyone help me make that work? I think it could be interesting for many who want to have this kind of reset circuitry for the cem3340.
Image

Thanks in advance!

Flub
Learning to Wiggle
Posts: 6
Joined: Fri Mar 06, 2020 1:39 pm

Re: CEM3340 hard sync / reset phase

Post by Flub » Mon Mar 09, 2020 6:10 pm

I found the solution !!! It was necessary to remove C2. It seems that for that EMM Spectrum Synth it should only sync on higher Frequencies.
Thats the final circuit i am using. Image

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mrand
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Re: CEM3340 hard sync / reset phase

Post by mrand » Mon Mar 09, 2020 7:16 pm

Nice job!
I gave up on 3340 sync because every option I tried seemed too tricky to trigger, and/or was just plain lousy sounding.
Any thoughts on how your version sounds? (aside from solving your click problem). It certainly looks ideal for LFO duties.
Colin
--ssdp--

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