Being mindful of crosstalk when drawing layouts

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Kevin Mitchell
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Being mindful of crosstalk when drawing layouts

Post by Kevin Mitchell » Mon Feb 15, 2021 9:30 am

I know only little information on the subject of crosstalk and that I must have been lucky so far in not having to deal with it.
As I'm refining a layout with a decent amount of switching ICs and off board connections I'm starting to get paranoid about crosstalk being a problem. So I'm here to raise some questions. While I have a fairly basic understanding of the following I'm hoping folks here can set the record straight.

-What is crosstalk? (what is it and what causes it?)

-Is it a common issue with layouts? (do people combat crosstalk with new designs often?)

-How do we mitigate it? (methods for avoiding it while designing a layout and also methods for fixing a board already suffering from it?)

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Re: Being mindful of crosstalk when drawing layouts

Post by Kent » Mon Feb 15, 2021 9:40 am

Read up on Tim Stinchcombe's rundown of the Plan B M9 mixer.

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Re: Being mindful of crosstalk when drawing layouts

Post by Rex Coil 7 » Mon Feb 15, 2021 9:52 am

Kent wrote:
Mon Feb 15, 2021 9:40 am
Read up on Tim Stinchcombe's rundown of the Plan B M9 mixer.
... http://www.timstinchcombe.co.uk/index.php?pge=m9 ...
5U MODULAR NORMALIZING PROJECT (for your entertainment) viewtopic.php?t=78836&highlight=
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Re: Being mindful of crosstalk when drawing layouts

Post by MikeDB » Mon Feb 15, 2021 10:21 am

Kevin Mitchell wrote:
Mon Feb 15, 2021 9:30 am
I know only little information on the subject of crosstalk and that I must have been lucky so far in not having to deal with it.
As I'm refining a layout with a decent amount of switching ICs and off board connections I'm starting to get paranoid about crosstalk being a problem. So I'm here to raise some questions. While I have a fairly basic understanding of the following I'm hoping folks here can set the record straight.

-What is crosstalk? (what is it and what causes it?)

-Is it a common issue with layouts? (do people combat crosstalk with new designs often?)

-How do we mitigate it? (methods for avoiding it while designing a layout and also methods for fixing a board already suffering from it?)
Identify your critical tracks by sensitivity - I class them in three grades and don't care. The highest grade gets a ground track either side of it separated from the ground plane except on vias at both ends. Second makes sure there are no parallel tracks for long distances, then gets ground plane but with special attention - see later. Third just gets ground plane with the possibility of parallel tracks but spaced as much as possible.

Then assuming two layers, ground plane everything else - top and bottom.

Finally connect the two ground plans together with vias. Lots of arguments on how best to do this. Either you splatter them everywhere - many PC cards do this where you can see a regular grid of vias, or better still work out where the circulating currents are in the ground and encourage them away from sensitive areas by strategic placing of the vias.

If you're using 4 layers, the rules are a bit different, but not wildly so.

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Re: Being mindful of crosstalk when drawing layouts

Post by EATyourGUITAR » Mon Feb 15, 2021 11:12 am

coaxial cable eliminates crosstalk. a single channel strip in a metal cage eliminates crosstalk. shielding is good. ground planes are good but not %100. if you have a 4 layer or 6 layer board then ground planes can actually do it all. but on a 2 layer board not so much. it is inevitable that there will be parallel traces on a 2 layer PCB without stacking PCB's. the best thing you can do is try not to drive large loads with large AC currents. understand a little bit about how capacitors are made and how transformers are made. the schematic symbol for a capacitor is two metal plates air gapped so that only AC can pass. this is known as AC coupling. in RF the engineers like to talk about transmission lines. an schematic symbol for a transformer without a core is two coils of wire that are air gapped. again this is blocking DC while coupling AC. these concepts work in 3D so there is a limit to understanding it as a 2 layer 2.5D PCB design.

another source of crosstalk has nothing to do with induced current through air gapped copper conductors. the second worry is common impedance coupling. the idea that the return current path for an unbalanced signal is the same ground plane as something else. this can happen with power planes as well as ground planes. the higher the impedance to any ref pin or power pin, the greater the chance that the voltage there will be modulated by the AC current flowing through the copper conductor. having big fat traces for power with star distribution is a common way to address the problem. daisy chain distribution of power is a bad idea unless you actually understand where and how you can do it without causing problems.
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Re: Being mindful of crosstalk when drawing layouts

Post by 60hz » Mon Feb 15, 2021 10:24 pm

4ms have an article on their blog about PCB crosstalk:
http://4ms.org/?p=441

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Re: Being mindful of crosstalk when drawing layouts

Post by Kevin Mitchell » Wed Feb 17, 2021 2:49 pm

Thanks guys! That last link was very helpful. Math and all!

Let's break it down.
-What is crosstalk? (what is it and what causes it?)
It's when the characteristics of an oscillating signal show up on parallel signal - in this case we're taking about circuit board tracks (both next to and beneath). Parallel tracks act as a capacitor and capacitors pass/conduct higher frequencies easier than lower. The longer these tracks run parallel, the more capacitance & vulnerability they have. The main factors for crosstalk potential are the frequency of the signal, copper volume of the tracks, space between the tracks and also PCB material.

-Is it a common issue with layouts? (do people combat crosstalk with new designs often?)
It is clear that this is a potential issue with higher frequencies. So it would depend on the design. I can imagine this being a factor when routing clock and data signals. Though not as crucial with VCO outputs, it's worth taking the necessary precautions to avoid any artifacts in the audio signal when playing higher octave notes. So I'd like to say no - as we would probably see more inquiries about debugging such a problem for new layouts. But it can and has happened.

-How do we mitigate it? (methods for avoiding it while designing a layout and also methods for fixing a board already suffering from it?)
Try to isolate high frequency signals or signals that have the potential to reach high frequencies. Surround the signal with a healthy ground plane or track. Do not cross these signals over others unless it's isolated with a ground route (more possible with multi layered PCBs). If trying to remedy a PCB with a crosstalk problem, cutting the track at the source of the signal and route with a shielded cable is the easiest method to salvage the board.



An example of caution that I will try;
A 3340 VCO design on a 2 layer PCB with it's 3 oscillating outputs (saw, tri and square) routed to somewhere - whether that be an IC, switch or connector. Assure the tracks do not cross other signals and are isolated with a ground plane beneath and next to it. Of course that would mean making sure you've got a healthy ground - otherwise it's only adding to the potential problem of crosstalk.
Also, skinny tracks help. Less copper & more space = less potential.

Also with this knowledge I shouldn't be surprised if I were to see let's say... glitches in a breadboarded Z80 computer - considering the amount of data wires/jumpers involved.


Sounds about right?

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Re: Being mindful of crosstalk when drawing layouts

Post by MikeDB » Wed Feb 17, 2021 5:53 pm

"Do not cross these signals over others unless it's isolated with a ground route"

I'd add, if they cross over at exactly 90 degrees then crosstalk is minimized. Douglas Self goes into crosstalk in great detail in Chaps 21 & 22 of his audio design book.


"glitches in a breadboarded Z80 computer"

Oh boy yes. We were still discovering about this sort of stuff when the first uPs appeared. The r.f. guys had known it for years but analogue and digital people never talked to one another :-)

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Re: Being mindful of crosstalk when drawing layouts

Post by ZTX500 » Wed Feb 17, 2021 7:13 pm

The 4ms example linked above refers to a 0.01pF coupling between traces leading to 2nA of current injected. In their example, this gets converted into a nontrivial 0.2V signal because the impedance of the trace being coupled to is 100Mohm. This seems unusually high - perhaps typical of some nodes in S&H circuits but not much else in modular? For a 100kohm impedance, 0.2nA becomes a more reasonable 200uV, or -88dBV on a 5V signal.

This suggests that:
  • crosstalk is likely to be more of a problem at high-impedance nodes (where the signal current is very small)
  • reducing impedance (e.g. reducing all resistor values in proportion in an inverting op-amp mixer) could be a mitigation for crosstalk.

Are either of these correct or useful ways to think about mitigating crosstalk?

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MikeDB
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Re: Being mindful of crosstalk when drawing layouts

Post by MikeDB » Wed Feb 17, 2021 7:36 pm

Any very high impedance node such as a sample and hold should have a guard ring around it which mostly removes any crosstalk worries.

Reducing impedance always reduces crosstalk and noise. It just makes everything hot instead. 5532s rule OK !! :-)

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Re: Being mindful of crosstalk when drawing layouts

Post by ricko » Mon Feb 22, 2021 3:26 am

So is this right?

There are two physical issues: inductive interference (a purely electro-magnetic effect) and signal bleed (a purely electrical/materials effect). These can be the mechanisms for to generate crosstalk and capacitive coupling, which if affecting the feedback of an amplifier, can cause unwanted oscillations.

These will tend to show up when two parallel tracks, one of which may sometimes have a relatively high-level signal while the other may sometimes have a relatively low-level (or no) signal, are relatively close to each other for some distance.

There are various fixes: from prevention (e.g. not allowing long close parallel traces) to cure (e.g. filter caps on op-amp feedback loops). The bleed issue has improved with modern PCB material, and the induction issue has improved with better layout practises, but neither is necessarily eliminated.

RULES OF THUMB

One rule of thumb that can be used for non-experts is to avoid laying out PCBs by hand, but use autorouting with appropriate settings. Why have to know stuff if the machine can often avoid it? (Just kidding.)

For example, in FreeRouter/KiCad you might consider the following placement/routing ideas:

A. Enable the option that tracks on both sides of the board are generally run diagonally to each other;

B. Set the clearance matrix for normal signals not as the default 1 x the track width, but e.g. 1.5 x. e.g. 12mm not 6 mm or 8mm. If you are using a 2-layer board with fairly sparse components, why not make it even larger, e.g. 20mil? (I also put a bigger clearance between 12V, -12V, 0V and 5V tracks and anything else: 20 mil. No harm that I can see??)

C. Or you might care to create a new class for tracks that may carry low-level signals, and assign a larger clearance for them. As well, if the low-level signal is caused because it comes after a resistor (such as the input), place that resistor to minimize the size of that low-level signal.

D. you place components so that you don't get vias (this is my own personal rule of thumb, and not 100% reasonable: a via indicates there are lots of things getting in the way, which may suggest a long track might be made, so if shifting a component to more in-between its connection points results in less track, it can be good.)

Then there are other rules of thumb regarding circuit design rather than board layout:

E. Don't run too "hot" a circuit. E.g. run internally at 2V PP not 10V PP and amplify at the output buffer, if the circuit permits. Nowadays we have so many low-noise op-amps we don't need to have hot signals internal to circuits to reduce noise.

F. Avoid op-amps with too fast a slew rate: they just invite HF oscillation. (Draw your PCBs with holes or pads to take filtering caps on the feedback loop of op-amps, so they can be installed later if needed, rather than throwing away the PCBs.)

Others? (Or are the above bogus in some situations?)

I guess there should be some rule of thumb about the 100k feedback resistor causing oscillations, which is what was claimed to caused be the location of the problem in the thread about the plan 9 4 channel mixer? What might that rule be?

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Re: Being mindful of crosstalk when drawing layouts

Post by ZTX500 » Mon Feb 22, 2021 7:26 am

The resistor causing oscillations in the Plan 9 mixer isn't the feedback resistor - it's a resistor connected to the non-inverting input of the op-amp to try to minimise DC offset. This creates a fairly high impedance at the non-inverting input, which is the problem here, since the high impedance node exhibits a large voltage variation even when the current injected into it by capacitive coupling is quite small. The solution is to replace this resistor with a wire link, which will shunt most of the coupled noise to ground. (As Tim Stinchcombe points out, in the Plan 9 mixer this resistor does almost nothing to correct the DC offset anyway, so omitting it is no big deal.)

On another note, I don't believe that point E is quite correct. If all voltages and currents in a circuit are reduced by the same factor, by just by attenuating the input, the crosstalk will not be significantly affected. I think it is the ratio of typical signal voltage to typical signal current that is important. If all the impedances in the system get smaller (decreasing resistor values, increasing capacitor values) then the current injected though coupling/crosstalk is less significant compared to the signal levels.

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Re: Being mindful of crosstalk when drawing layouts

Post by ricko » Mon Feb 22, 2021 8:44 am

Yes, for E I was thinking of the case where an OTA with a padded-right down signal is at the core.

So the input might be 10VPP, but the OTA core inside (e.g, LM13600) only takes less than 100mV: safer to have the intermediate circuits not working at full 10VPP (and any tracks taking that 50mV should be short and distanced). Though are the differences between 50mV and the rest of the circuit so great that crosstalk etc from an adjacent 2VPP signal is not that much different than from a 10VPP signal?

Probably, although common, it is too specific a case to be made into a useful generalization?

For the replacement of the resistor by a wire, could I say that is cure (reducing the effect of this noise in the wrong location) rather than prevention (not having so much coupling in the first place)? In which case, what is the design rule of thumb to be used? Keep the tracks to op-amp inputs quite apart, except for voltage followers?

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Re: Being mindful of crosstalk when drawing layouts

Post by jorg » Mon Feb 22, 2021 9:32 am

ZTX500 wrote:
Wed Feb 17, 2021 7:13 pm
  • crosstalk is likely to be more of a problem at high-impedance nodes (where the signal current is very small)
  • reducing impedance (e.g. reducing all resistor values in proportion in an inverting op-amp mixer) could be a mitigation for crosstalk.

Are either of these correct or useful ways to think about mitigating crosstalk?
Worst case is a high-amplitude, low-impedance node, coupling to a low-amplitude, high-impedance node. The high-amplitude, low-impedance node will have lots of voltage swing, which can capacitively couple, and high current, which can induce currents in nearby conductors. The low-amplitude, high-impedance signal will easily pick up both of these types of coupling.

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