Trouble with triangle to ramp circuit

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5xbman
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Trouble with triangle to ramp circuit

Post by 5xbman » Thu Feb 18, 2021 1:22 pm

Greetings wigglers,

I'm new here (been playing with electronics for many years and got into synths a while back.)

I've been working on designing and building a VCO. Said VCO generates a triangle and I'm working on the circuit that converts to a ramp. This is the circuit I'm using:
Screenshot at 2021-02-18 13-04-16.png
Screenshot at 2021-02-18 13-04-16.png (7.39 KiB) Viewed 224 times
TRI is the triangle wave, PHASE is a square wave to invert part of the triangle to make a ramp.

Trouble is that whenever the FET turns on or off, there's a glitch in the ramp. You can easily see one of the glitches half way up the ramp.
DS1Z_QuickPrint2.png
I've tried a load of different things to try to cure this. Anyone have any idea what causes this and how to fix it?

Thanks in adavance for any insight.
-- Martin

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KSS
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Re: Trouble with triangle to ramp circuit

Post by KSS » Thu Feb 18, 2021 1:49 pm

Welcome to MuffWiggler, 5xbman!

It's normal.

Typically 'fixed' with a smoothing capacitor. Hint: What does the square wave look like at its direction changes?

What would reducing the values of r115,122,125 around U105 do?

What if you paralleled a second 7002?

Is 100K the ideal value for R125?
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Re: Trouble with triangle to ramp circuit

Post by jorg » Thu Feb 18, 2021 2:48 pm

If you're OK with the ramp being an octave above the triangle, don't add the offset which splices the two rising segments into one segment. Then the "glitch" becomes just one of the normal saw edges.

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Re: Trouble with triangle to ramp circuit

Post by EATyourGUITAR » Thu Feb 18, 2021 3:19 pm

I don't understand the phase relationship or the octave doubling because I'm dumb and I can't see the analog comparator circuit. Can you post the other part? If this is inverting the waveform at the top and bottom of the triangle then would it also be sensitive to the amplitude of the triangle? I understand if you have a DCO this is no problem.
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Re: Trouble with triangle to ramp circuit

Post by 5xbman » Thu Feb 18, 2021 8:03 pm

KSS wrote:
Thu Feb 18, 2021 1:49 pm
Welcome to MuffWiggler, 5xbman!
Thanks, good to be here!
It's normal.
I was wondering if someone would say that ;) That's actually OK, to some extent -- seems to be the kind of thing that gives analogue synths their unique place in the world. But I could forsee problems if I tried to use the same circuit for an LFO, which I was thinking of doing. I could also see problems if trying to use a ramp that looked like that for PWM.
Typically 'fixed' with a smoothing capacitor. Hint: What does the square wave look like at its direction changes?
There's a little bit of rounding at the top of the rising edge. I wasn't too worried but I think it might delay the turn on of the FET. But that only seems to be noticeable at higher frequencies.
What would reducing the values of r115,122,125 around U105 do?
I tried setting them all to 10k -- same result.
What if you paralleled a second 7002?
I will have to try that.
Is 100K the ideal value for R125?
The best results so far seem to be with R115 and R22 at 100k, and reducing R125 to 4.7k. I can try reducing it some more but there's only so far you can go!

Interestingly, if I look at the waveform at the drain of the FET, the glitch is there, i.e.the voltage is dipping below ground. Not sure how that's happening.

Anyway, thanks for your suggestions. I shall continue to play with it and report any useful findings.

-- Martin
-- Martin

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5xbman
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Re: Trouble with triangle to ramp circuit

Post by 5xbman » Thu Feb 18, 2021 8:04 pm

jorg wrote:
Thu Feb 18, 2021 2:48 pm
If you're OK with the ramp being an octave above the triangle, don't add the offset which splices the two rising segments into one segment. Then the "glitch" becomes just one of the normal saw edges.
Interesting idea but not really what I want here. I think the sqaure wave may need to be 90 degrees out of phase with what I'm feeding it though -- have to think about that some more.

-- Martin
-- Martin

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Re: Trouble with triangle to ramp circuit

Post by 5xbman » Thu Feb 18, 2021 8:07 pm

EATyourGUITAR wrote:
Thu Feb 18, 2021 3:19 pm
I don't understand the phase relationship or the octave doubling because I'm dumb and I can't see the analog comparator circuit. Can you post the other part? If this is inverting the waveform at the top and bottom of the triangle then would it also be sensitive to the amplitude of the triangle? I understand if you have a DCO this is no problem.
You're taking (say) the leading edge of the triangle ang leaving it alone, then taking the trailing edge and inverting it. So for every one cycle of the triangle you get two cycles of ramp. Make sense?

-- Martin
-- Martin

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Re: Trouble with triangle to ramp circuit

Post by EATyourGUITAR » Thu Feb 18, 2021 10:19 pm

Yes exactly but then you have two analog comparators to detect the phase of the triangle. This must be adjusted to be just below the min and max of the triangle so that they represent very close to theta 0 theta 180. Is it done with analog comparators or is it software controlled? How do you extract phase information? Or maybe you already have the phase information because your VCO is a flip flop integrated into a triangle? This is what I don't yet know about the rest of your circuit.
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Re: Trouble with triangle to ramp circuit

Post by Synthiq » Thu Feb 18, 2021 10:20 pm

5xbman wrote:
Thu Feb 18, 2021 8:03 pm
Interestingly, if I look at the waveform at the drain of the FET, the glitch is there, i.e.the voltage is dipping below ground. Not sure how that's happening.
The 2N7002 has a 30pF gate capacitance. When the transistor turns off, the charge on the bottom plate of that capacitance will exit the transistor partly via the source and partly via the drain so I'm not surprised if the drain is pushed down. The opposite seems to happen on the other edge as there is a small peak at the top of the ramp.

The 2N7002 on-resistance is like 3-4 ohm and much lower than you need to the circuit to work. If you can find a mosfet with less gate capacitance and somewhat higher on-resistance you may be able to reduce the spikes you see.

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Re: Trouble with triangle to ramp circuit

Post by 5xbman » Thu Feb 18, 2021 11:14 pm

EATyourGUITAR wrote:
Thu Feb 18, 2021 10:19 pm
Yes exactly but then you have two analog comparators to detect the phase of the triangle. This must be adjusted to be just below the min and max of the triangle so that they represent very close to theta 0 theta 180. Is it done with analog comparators or is it software controlled? How do you extract phase information? Or maybe you already have the phase information because your VCO is a flip flop integrated into a triangle? This is what I don't yet know about the rest of your circuit.
It's actually a single analog comparator with hysteresis so it functions as a flip flop. The arrangement works very well and gives me a nice symmetric triangle. But that's not the part I'm having trouble with. The square wave coming out of the comparator is also trouble free. The issue appears to be with the FET that controls the invert/non invert of the op amp.

I'm not really interested in having the ramp an octave above, so I haven't given that particular arrangement a lot of thought. But I think it might work. Is that what you're asking about? As I say, this is not something that interest me at least at the moment.
-- Martin

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Re: Trouble with triangle to ramp circuit

Post by 5xbman » Thu Feb 18, 2021 11:15 pm

Synthiq wrote:
Thu Feb 18, 2021 10:20 pm
5xbman wrote:
Thu Feb 18, 2021 8:03 pm
Interestingly, if I look at the waveform at the drain of the FET, the glitch is there, i.e.the voltage is dipping below ground. Not sure how that's happening.
The 2N7002 has a 30pF gate capacitance. When the transistor turns off, the charge on the bottom plate of that capacitance will exit the transistor partly via the source and partly via the drain so I'm not surprised if the drain is pushed down. The opposite seems to happen on the other edge as there is a small peak at the top of the ramp.

The 2N7002 on-resistance is like 3-4 ohm and much lower than you need to the circuit to work. If you can find a mosfet with less gate capacitance and somewhat higher on-resistance you may be able to reduce the spikes you see.
Thanks, this makes sense. I will look to see if there's an alternative part that might work better.

-- Martin
-- Martin

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Re: Trouble with triangle to ramp circuit

Post by EATyourGUITAR » Fri Feb 19, 2021 12:09 am

the reason I asked is that I do think it is relevant what the capacitance is on your square wave. basically what was already said about the 30pf from the gate of the FET adding slew.the rise time should be near zero. the slew rate of the opamps should be better than a TL074. TL074 is not really a wide band opamp. when you use a TL074 to do anything with square waves, you can draw enough surge current through the die to manifest as noise in the other two channels of the TL074. for this reason, a quad opamp should not be used here if you really want to clean things up. but that is really two different things. quad opamp problems vs slew rate problems. none of this matters if you have cacitance on the FET. but even if you solve that problem, you also need fast rise times from your square wave. that depends on how much current you can drive from the output of your comparator. if you are using a single comparator with a lot of hysteresis that makes me think that something is operating with positive feedback through a resistor. the current used to drive the fet is also being used to drive this positive feedback. if you buffer it so that your board layout has the output of a schmitt trigger very close to the FET, this may be enough to drive the capacitive load with good rise times.

I think you should zoom in on this discontinuous spike so we can see if it skews left or right. I wonder if the input bias current to the opamp changes depending on the phase since that is a 3 way node with a resistor, a FET, and a jfet input on the TL074. the impedance through the FET goes from 4 Ohms to 100M. with a better opamp your input offset and input bias current could be an order of magnitude lower.
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Re: Trouble with triangle to ramp circuit

Post by EATyourGUITAR » Fri Feb 19, 2021 12:15 am

also, you could throw everything in the trash and use this IC as a four quadrant multiplier for $1. this way the signal is close to 0v when it goes through zero on the multiplier. the error amplitude would be directly tied to the time error of your square wave. you can also use different techniques to track the change of direction of the triangle.

https://www.mouser.com/ProductDetail/ON ... 52BQ%3D%3D
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Re: Trouble with triangle to ramp circuit

Post by Synthiq » Fri Feb 19, 2021 1:12 am

In the schematic above, the gate is driven via a 47kohm resistor so the TL074 output current will be small so it is unlikely it will affect any of the other amplifiers in the same package or the switching times.

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Re: Trouble with triangle to ramp circuit

Post by Troubleshooter » Fri Feb 19, 2021 9:25 am

My Yusynth VCLFO also suffers from a similar switching slowliness. They are saw core and the spikes appear on the triangle and sine peaks. A filter is provided in the original design to simply filter them out but also lowers the amplitude on higher audio range frequency's. I found maximizing discharge currents in the core (thick pcb trace, good quality switches for range switching etc...) minimizes the problem but it never totally disappears. It is simply a "design error").

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Re: Trouble with triangle to ramp circuit

Post by devinw1 » Fri Feb 19, 2021 12:01 pm

You can probably make the glitch a little less noticable by lowering the impedance at U105B and putting a small cap in parallel with the feedback resistor (10-47p ish). Beyond that you are limited by the FETs effects (charge injection is one thing). That's why I usually use a spare CMOS switch instead of a FET there. It works awesome. Glitch free for all effective purposes.

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