Trying to clock a BBD with a PT2399 (got stuck)

[Jonachi]

Dear DIY Synth Lords.


Completly stuck here, trying to clock a BBD chip with the output clock of the PT2399 chip. I named this the Clazone delay since it is suppose to have a delay withing a delay and the order of the 2 delays are switchable. I used the good old divider down the clock chematic floating the tinternet on how to get a led to blink and show the tempo of the PT2399 as the input to the 3102. It does it's thing and is outputing 2 clocks to the BBD (as should)

however, the PT2399 part is working as expected, the bdd part is dead silent. If I probe the wet side of RV7 I hear the clock of the BBD ever so slightly, but no delays. My guess is that there is something wrong with the clock signal to the BBD that needs to be tweaked further. I read the datasheet (http://www.radio63.narod.ru/page/download/V3205.pdf) severl time already but can't find an answer.


Any help would be apreciated. Schamtics included below.

[fitzgreyve]

First thing to check is that you are getting (opposite phase) square waves at the CP1 and CP2 outputs of the MN3102?

Also, what is the output drive capability of the PT2399 clock out, as you are feeding this into a 2k2 resistor.?

Ahh, you've said this is working - next thing is to check for signal at the two outputs of the BBD - ideally with a scope (there will be a lot of clock noise, but you can tell if there is signal within it.)

Are your 4040 dividers reducing the (megahertz range) PT2399 clock sufficiently to get a (10's of kilohetz range) clock for the BBD ?

[Jonachi]

the signal on the outputs seems to be at 1.8v with a really fast clock, slowing down the pt2399 the output jumps between 1.7v and 1.9 which should be the clock noise I'm seing? I can hear and see the input signal on leg 7 on the BBD chip so it should rceive it.

I asume the MN3102 is doing its job cos I can see the clock coming in and out of it, also I can see it reach the BBD clock inputs. However, it is hard for me to to know that they are in opposite phase. how does one chck that or can one asume that if a MN3102 is outputing on both ouput chanels it HAS to be in opposite phase?

Thanks for your kind help and answers.

[Jonachi]

need any help I can get on this one. Completly stuck at the moment.

[fitzgreyve]

THings that can stop a BBD working:
1. both clock inputs present and of correct (opposing) phase, and in correct freq range
2. Vgg level correct
3. input signal OK
4. signal outputs OK
5. output reconstruction filter(s) designed and working OK
6. Duff/fake BBD chip

The basic principle is "assume nothing" - here's how I'd look at it:
(0. is power correct - looks OK on the schematic, measure and confirm).
1. Looking at the MN3102 block diagram, I think it's a fair assumption (but not absolute proof!) that if both CP1 and CP2 are present, they have to be of opposite phase.
Have you any way of measuring the clock freq to check the dividers are working (not obvious what division you are using)?
2. You are using the Vgg output of the MN3102, so that should be OK, but measure and check at BBD pin 8
3. With audio input, check for audio signal at BBD pin 7. Then, without signal input, adjust for (roughly) correct bias voltage at pin 7 - if the bias is way off, you tend to only get DC signal passing thro' the BBD
4. Check for signal output at >both< outputs - pin 3 AND 4 of the BBD - there wil lbe a lot of clokc noise, but some signal should be audible
5. If (4) is OK (at both outputs). Trace the audio signal through the output circuity: a step at a time from R42/R46 thro IC9B, IC3A, to IC3B
I'm not clear on the output filter design: R47/C21 is 4.8K 6dB LP, IC9B has gain approx x10, IC3A gain not clear, R55-C29 is 7k 12dB LP, IC3B gain unclear.
In most designs I've seen before (and used) C22 would generally be closer to 100n, and I'm not sure of the effect of C20. IC3A (to me) appears redundant ?
6. If everything else is OK, this is always a possibility!

[Kevin Mitchell]

As suggested, I would verify that there's indeed dual inverse clock pulses coming from the 3102. Ideally with a dual channel oscilloscope.

Are the 3205 and 3102 coolaudio chips?
If not, I would be suspicious - especially of the MN3205. Those aren't as common nowadays and are more often fake than legitimate & functional. Could also just be a damaged BBD.

But I must note that I haven't seen the clock chip set up like that before. What are you using as a reference? Certainly not the datasheet.

[Troubleshooter]

On your schematic CP2 is connected to ground. I hope you didn't autoroute it into a pcb?

[Kevin Mitchell]

On your schematic CP2 is connected to ground. I hope you didn't autoroute it into a pcb?

Good catch. So there's half the sample rate since there is no dual inverse clock cycles - the signal is only being passed through one of two channels -then the output is being pulled even lower through the mixing node.

[fitzgreyve]

Well spotted - I missed that - OP needs to check for clock pulse(CP2) on MN3102 pin 4 and on BBD pin 2.

[pjbulls]

I haven't seen the clock chip set up like that before. What are you using as a reference? Certainly not the datasheet.

The BBD circuit seems to be a copy of the EricaSynths module, minus the CP2 into ground connection. The actual clock input into the MN3102 is also very different, obviously.

e:
there's some previous discussion on the PT2399 clock out here and elsewhere, this seems to be the most informative (or at least has a very similar circuit to the OP's).

Note that you apparently need to use 74HC4040 chips, the regular CD4040 is not fast enough to keep up with the PT2399 clock out.

[Jonachi]

Wow, thanks to you all.

yes, the erica synths bbd was the inspieration for that part of the circuit.

I can't really see the CP2 going to ground. It just looks like that when the lines cross but I can't see a junction. Will measure it though to see if it is connected to ground somewhow? I know I've measured it on both the clock and bbd chip so it isn't completly shorted at least.

The regular cd4040 seems to be doing just fine. I can see and hear the clock post cd4040 on the board, no matter how fast or slow I drive it with the pt-chip.

[Jonachi]

Just checked the gerbers and there is no connection to grund between the cp2 on th clock or bbd. just a single trace connecting the two nothing else.

[pjbulls]

There is (probably by mistake) a connection between CP2 and ground in your schematic:


If you are building this on a breadboard or so and using the schematic to keep track, no issue (yet). If you turned this schematic into a PCB/gerber then the damage is already done, because those two nets should not be tied together. Maybe a bit of bodge wire can fix it?

[Jonachi]

That’s so wierd. My schematics dont look like that and there is no connection to gnd on my boards. That must have been kikad auto-routing when I exported the pdf, and then I cleaned it up?

Anyways it is not the problem. So I need to keep looking.