nw2s::dsp development platform up and running!

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scottwilson
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nw2s::dsp development platform up and running!

Post by scottwilson » Mon Jun 29, 2015 8:37 am

So to clarify the difference in the nw2s::b2 and the nw2s::c, I'm going to rename it to the nw2s::dsp to be clear what it's supposed to be - a no compromise 4 in 8 out DSP module!

Anyway, excited to have my development platform for it up and running!

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dadek
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Post by dadek » Mon Jun 29, 2015 10:59 am

:guinness:
Congrats Scott!
:tu:

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scottwilson
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Post by scottwilson » Mon Jul 06, 2015 8:13 am

So I have a development system for both the ADSP21489 and ADSP21469. The difference is that the 21469 has a DDR2 RAM interface and the 21489 has an SDR RAM interface.

In the audio world, reverbs are very dependent on memory bandwidth. The more delay lines you can get in and out of external RAM, the better your reverb is going to sound... or so the theory goes.

I'm not quite ready to start developing my own algorithmic reverbs yet, so decided to try a convolution reverb. Using an overlap-add algorithm, the length of the impulse response is directly related to how many blocks of frequency-domain audio and impulse response you can get from external memory to internal ram for multiply accumulates. On a processor like the SHARC, the time spent doing time domain to frequency domain transformations becomes trivial in comparison.

So with SDR RAM, I was only able to get about 1.5s impulse response and the memory bus was maxed out - No headroom for any other processing. It's possible I could do some further optimization, but it's doubtful you can do much to get over the hard limit of memory bandwidth.

However, with DDR2 RAM, I was able to process a 3 second stereo impulse response with headroom left over for a spare delay line or two.

Woohoo. Except that there's one issue: packaging. The 21489 (SDR) uses a leaded package which is a little easier to prototype in that you can reasonably solder one by hand - if you've got some skillz. The 21469 (DDR2) uses a 1mm pitch BGA - which just isn't prototypable by hand, sadly. Additionally, all of the 2Gbit DDR2 RAM is BGA.

So be it. I've tasted the speedier RAM and it's going to be hard to justify not going all the way.

Now that nw2s::dsp POC is closer to done, I'm getting back into 1.1 and the b2 prototype. I'll throw some of my convolution reverb onto some of the upcoming demos.

I've been posting smaller/quick updates on facebook, so follow me there if you want to get some news more often:

https://www.facebook.com/nw2smodular

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