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Serge Gator/Divide Logic Question
MUFF WIGGLER Forum Index -> Buchla, EMS & Serge  
Author Serge Gator/Divide Logic Question
syncretism
Video: https://www.youtube.com/watch?v=oXi9ANBC4iQ






The VC Timegen Clock from my Gator is triggering a Variable Q filter with a simple, constant chain of pulses:

x x x x x x x x

If I patch the /2 output to the filter's 1 v/o input, I get, as expected, alternating hits, like:

x X x X x X x X


I would expect /4 to be something like

x x x X x x x X

But instead I'm getting:

x x X X x x X X

/5 gives me

x x X X X x x X X X

I get the same results whether I'm using the AND gate to ping that v/o input or not.


Am I just doing this wrong? I just want to accent every fourth hit (or whatever other number), and I'm confused by the "clustering" I see and hear. help
n3wt15
What you are trying to do, doesn't require using the Boolean logic, just take the pulse directly from the Pulse Divider.
wavecircle
It's the way the STS pulse divider works, as far as I remember it holds high for longer than one pulse cycle. I don't think the CGS one works the same way though could be wrong.
syncretism
n3wt15 wrote:
What you are trying to do, doesn't require using the Boolean logic, just take the pulse directly from the Pulse Divider.


It’s the same behavior, either way; I’m not seeing a pulse every N gates, which is what I’d expect, but my expectations could be wrong.
wavecircle
Can you plug it into a scope? Even one on your computer would be fine.
c411vm
I would have thought that you should use the divider output (/4) directly if you want to trigger something on every fourth clock cycle (as n3wt15 said), but you mentioned that doesn't work as expected.

As for an explanation of what might be going on in your patch, the observations are consistent with the pulse divider achieving each of the divisions in the following way:

/2: high for one clock cycle, low for one clock cycle
/3: high for two clock cycles, low for one clock cycle
/4: high for two clock cycles, low for two clock cycles
/5: high for three clock cycles, low for two clock cycles
/6: high for three clock cycles, low for three clock cycles
/7: high for four clock cycles, low for three clock cycles
/8: high for four clock cycles, low for four clock cycles

If this were the case, given that the divider and clock output are being ANDed, it would explain why the final output is a pulse at the frequency of the clock when the divider output is high.

Disclaimer: I don't own any Serge gear.
the bad producer
The CGS one doesn't do this, I just happened to have one here right now and checked out everything and it's 'what you would like/expect' from a divider!
syncretism
Wavecircle called it, as did a pal who checked his own Gator offline - it appears that the divider output (or the gate signal from the VC TGO) is high for too long. When I patch the /n output to a DTG patched for a fast slope, I get the behavior I expect. This isn't an ideal use for the transient generator, so I hope I can get the same effect by using the Gator's comparator.

Thanks, all!
J3RK
Some dividers will increase in gate length based on the division, which is what you're seeing. You might be able to use an AND gate with another division (or the original clock) to normalize those pulses. (though it might not be perfect)

Edit: I wasn't able to see the video earlier. Just went by the description, and didn't quite get it. Yeah, that's odd behavior, and not what I'd expect. What I mentioned above won't really help in this case.
GrantB
syncretism wrote:
Wavecircle called it, as did a pal who checked his own Gator offline - it appears that the divider output (or the gate signal from the VC TGO) is high for too long. When I patch the /n output to a DTG patched for a fast slope, I get the behavior I expect. This isn't an ideal use for the transient generator, so I hope I can get the same effect by using the Gator's comparator.

Thanks, all!


If this is the case, can you change the gate length from the TGO with the VC in?
syncretism
GrantB wrote:
If this is the case, can you change the gate length from the TGO with the VC in?


Not without changing the speed of the pulses, I'd think.
n3wt15
When I had a gator, it did not behave like that, so something is up.
Borellus
syncretism wrote:
Video: https://www.youtube.com/watch?v=oXi9ANBC4iQ






The VC Timegen Clock from my Gator is triggering a Variable Q filter with a simple, constant chain of pulses:

x x x x x x x x

If I patch the /2 output to the filter's 1 v/o input, I get, as expected, alternating hits, like:

x X x X x X x X


I would expect /4 to be something like

x x x X x x x X

But instead I'm getting:

x x X X x x X X

/5 gives me

x x X X X x x X X X

I get the same results whether I'm using the AND gate to ping that v/o input or not.


Am I just doing this wrong? I just want to accent every fourth hit (or whatever other number), and I'm confused by the "clustering" I see and hear. help


Yes, I get this "galloping" effect when I use the PULSE DIVIDER into the AND gate, as in your example --but not when I use the ÷N COMP as a pulse divider instead. Apparently, they operate differently.
GrantB
syncretism wrote:
GrantB wrote:
If this is the case, can you change the gate length from the TGO with the VC in?


Not without changing the speed of the pulses, I'd think.


Right, so you'd use the FREQ control to compensate. I don't have a TGC, but my understanding is that it's just a DUSG board in there:

Quote:
If the TRIG IN jack is connected to the TRIG OUT jack, the DSG will oscillate with a waveform and frequency set by the RISE and FALL knobs. A series of pulses will appear at the TRIG OUT jack, and the duty cycle (the time the pulse is high compared to when it is low in each cycle) is set by the RISE and FALL knobs. The FALL knob determine how long the pulse is low. When the DSG is in the RISE part of the cycle or when the output is zero or less, the output of the TRIG OUT will be high. In some applications, a pulse with a very long duty cycle will cause erratic triggering in other modules. If such a symptom occurs, try increasing the FALL time and decreasing the RISE time to get the same pulse rate.


So can you VC just the rise or fall time to change the gate length?
Borellus
GrantB wrote:
So can you VC just the rise or fall time to change the gate length?


I tried that. Still the same behaviour from the PULSE DIVIDER, regardless of TGC duty cycle, and I tried both sides of the TGC as a clock.
syncretism
GrantB wrote:
So can you VC just the rise or fall time to change the gate length?


High frequency with an offset patched to fall time yields the same results. I’ve been unable to get, say, x x x y x x x y without using the second half of the DTG.

GrantB
wow something weird about the divider then
syncretism
Borellus wrote:

Yes, I get this "galloping" effect when I use the PULSE DIVIDER into the AND gate, as in your example --but not when I use the ÷N COMP as a pulse divider instead. Apparently, they operate differently.


We have at least three different accounts of its behavior by past and current owners. neutral
Borellus
syncretism wrote:
Borellus wrote:

Yes, I get this "galloping" effect when I use the PULSE DIVIDER into the AND gate, as in your example --but not when I use the ÷N COMP as a pulse divider instead. Apparently, they operate differently.


We have at least three different accounts of its behavior by past and current owners. neutral


Honestly, I don't mind:

1) For most triggering purposes (triggering slopes, sequencer stage selection, filter pinging, etc.), it still works as expected.

2) The proportionally longer gate times mean that when driven at audio rates, used as a sub-oscillator, the PULSE DIVIDER outputs are always square waves.

3) The PULSE DIVIDER's longer gates, when combined with the ÷N COMP and LOGIC modules, makes for a diverse range of polyrhythmic possibilities... a feature which I use a lot.

...just my 2 cent's worth.
syncretism
Stop being so bloody reasonable, Borellus! wink
Borellus
thumbs up
Corrupt
Borellus wrote:
2) The proportionally longer gate times mean that when driven at audio rates, used as a sub-oscillator, the PULSE DIVIDER outputs are always square waves.


Excellent point. I now believe this to be the guiding rationale. And of course I have a couple of new patch ideas...
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