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Can an SSG be patched as clock multiplier/divider?
MUFF WIGGLER Forum Index -> Buchla, EMS & Serge  
Author Can an SSG be patched as clock multiplier/divider?
luketeaford
Is it possible to patch either side of an SSG as a clock divider or multiplier? I can get related rhythms from it using the coupler output and each cycle independently, but if there is a way to use it as an accurate and straightforward clock divider/multiplier, it's going over my head.
Navs
It should be possible to use it as a clock divider - see the Serge Fans site or Toppobrillo Sport Modulator manual for how.

IIRC on the SM one gets the divided clock from the End Out. It's accurate in the same sense that using a DSG or Maths can act as a clock divider, i.e. you'll have to fine tune it to get /4 etc. ratios. The great thing is that you can also get other divisions.

It's a similar concept to using the DSG or SM as a subharmonic generator ...
cygmu
I don't see a way to do that. You certainly can't do it in the same way that you would with a DUSG / VCS because there's no triggered cycle. (The cycling works by slewing the output of a comparator rather than by triggering a rise-fall.)
batchas
cygmu wrote:
I don't see a way to do that.

+1
Navs
From the Sport Modulator manual:

Quote:
VC divider/ cascaded dividers/ suboscillators- put 1 section of the SM in HOLD mode and set it to CYC- LE. clock it with an external LFO or VCO or some- thing. the END out is now a variable division of the input freq according to the RATE and CV. take that END out [or just the OUT itself] and send it to the other section of the SM in the same mode for another variable division. the OUTS are of course nice stair- cases to climb up and down. use as suboscillators


http://www.toppobrillo.com/sportmodulator2.html

Is this not possible on the SSG? It looks similar to the 'squashed S&H' example here: http://serge-fans.com/wiz_SSG2.htm

hmmm.....
Navs
Some more info: https://www.muffwiggler.com/forum/viewtopic.php?t=139824&highlight=
cygmu
Ahh I see. Thanks Navs!!! I should have known not to doubt you on something like this.

This is a nice patch, though it is not quite a regular clock divider. You get a gate every time the stepped side reaches its minimum voltage level (I think), and the number of samples that takes depends on the slew rate of the stepped side, and won't be an integer, so you might get e.g. a gate on the 6th sample, then one between the 5th and 6th, then on the 5th, then on the 6th again. The gate stays high until the stepped signal reaches its peak.


[EDIT: the above is impossible -- the gates must be in time with the clock pulses. I think the envelopes I was triggering were doing some further clock division. Anyway, it's a nice patch.]

Something like that anyway -- and it is definitely interesting.

Explicit SSG patch instructions:

patch stepped cycle to stepped input
patch main clock to stepped sample
wonky divided clock signal is at the stepped cycle jack.
Navs
Excellent. Glad it works!

I just tried the SM - it's regular once set.



Bottom, blue trace is the master clock.
luketeaford
Thanks, navs, and everyone for helping with this. Interestingly, I am still nowhere near close to this patch using JUST an SSG. Cycle from the stepped side is USUALLY a negative voltage, and only rarely (and not rhythmically) gives me what I'm looking for.

I can do this with Maths (and probably also with a DUSG when I get one), but I was curious if there is a way to get clocks from an SSG.

My goal here is to get two or more clocks from just a self patched SSG. Ideally these clocks have an integer relationship. I think if I had this, I'd get a third clock from COUPLER output just by nature of how it works (maybe it would be a copy of stepped's cycle?)
cygmu
luketeaford wrote:
Cycle from the stepped side is USUALLY a negative voltage, and only rarely (and not rhythmically) gives me what I'm looking for


That's odd, and interesting.

On my SSG (DIY CGS version) the CYCLE output is around 7V when the cycle is rising and -7V when it's falling. The smooth side is the same.

So the following patch gives three correlated clock signals:

Smooth CYCLE to smooth INPUT
Smooth CYCLE (clock 1) to stepped SAMPLE
Stepped CYCLE to stepped INPUT
Stepped CYCLE is clock 2.
Coupler is clock 3.

Clock 2 will be some kind of division of clock 1. It's not quite as even as the scope shots Navs posted -- it is very possible to have it come up after 2 cycles of clock 1, then again after 3, then 2, then 3 etc. (But what I said in a post above about gates coming on between pulses was just wrong and impossible -- I've edited the post now.)

The coupler clock 3 is a quirky off-kilter thing, kind of interesting but definitely not a division of the smooth clock 1.
luketeaford
cygmu wrote:

So the following patch gives three correlated clock signals:

Smooth CYCLE to smooth INPUT
Smooth CYCLE (clock 1) to stepped SAMPLE
Stepped CYCLE to stepped INPUT
Stepped CYCLE is clock 2.
Coupler is clock 3.


This works for me! This was the patch I started with, but was looking for a way to sync up clock 2 a little tighter. After playing with it and listening again, this is sufficient for my needs. thumbs up
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