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Whst is a good design for a supersonic VCO?
MUFF WIGGLER Forum Index -> Music Tech DIY Goto page 1, 2, 3  Next [all]
Author Whst is a good design for a supersonic VCO?
The ARP ProSoloist and the Roland SH3A VCO both run at around 64x the audio rate of the notes they play. They clock various dividers and gates.

The Roland uses a Programmable UJT and the ARP uses an odd servo mechanism for octave switching.

So I was wondering what would be the best approach in the modern era (for an analog VCO)? I saw that that AS3340 gives a maximum frequrency of 80k, which is perhaps not quite enough, but this does match the datasheets and what people have done... (128k max is more like it?)

Any suggestions from anyone, please? I guess the integrator reset time is critical, so would a tri vco be better than a saw design?

So for the actual designs raised so far:

* Tantak Sampler/delay VCO (1980s)
- tri core. diode ring alternation. 6x 8ves?
- square out. FET output buffer (switch)
- CA3096 expo converter. LM311 Comparator.
- 10kHz to 200kHz?? (or is it 500 to 31k?)
- (Followed by 16x frequency multiplier, for switched cap tracking filter)

* Digisound VCDO
-CEM3340 with small cap @32x audio
- Frequency doubler (IC3)
- 64 audio, max 10k = 640k ?

* Sergio Franco SalMar VCO (1971, 1974)
- saw core. FET buffer 10x 8ves?
- clock out
- 1971 version: uA726 expo converter. uA710 Comparator. 74121 One shot reset
- 1974 version: CA3046 expo converter w heating. uA710 Comparator. 74121
- 16x audio rate

* Roland SH-3A (1974)
- saw core. Programmable UJT
- square out. 3216 divider chip.
- divide by 1/2/4 for 8ve. divide by 1/2/4/8/16 for mixable waveshapes. Typical M8' therefore /8. Low note l32' /64.
- KCV biased fixed sharktooth for each transpose through comparator with LFO allows a PWM chorus effect.
- (Because use division for 8ve selection, don't need as wide tracking range.)

* ARP Pro-soloist (1972)
- divide 1/2/4 for 8ve. Preset 8ve /1 or /2. Mix waves at 64x audio. So typical 64x audio.
- tiny discrete saw VCO + expo: in only 4 trannies: 1PNP, 2xNPN, 1 UJT
--> Surely this is pretty dodgy for staying in tune???
- subsequent TTL 74xxx dividers and logic
- reconstruct saw to allow PWM effect from EG
- (Because use division for 8ve selection, don't need as wide tracking range.)

Ian Fritz' Double Dekka ultrasonic vco
Uses LM331 V/F converter chip

Plus potentially:

* Thomas Henry X4046 VCO (2010?)
- 2N3904 expo pair.
- 4046 PLL
- use HCT version of 4046 and faster caps to increase rate.
I know you specifically asked about VCOs so it might be that you're looking for as "analog" solution as possible, but as an amateur with no real experience in oscillator design whatsoever, my first intuition would probably be making the core either fully digital, or at least the integrator to reset with digital control (eg. a DCO type solution).

One of the forum members (Grumble?) has been experimenting a lot with DDS / waveform generator ICs with a low cost microcontroller for control duties (filling the wavetable RAM etc.). I suppose those could be clocked relatively fast, and then dividing down as necessary from there.
Inspired by the work of fellow wiggler Grumble, I've ordered some AD9833 breakout boards to be used with a microcontroller. Search for "AD9833" on this forum to find his threads, there's some code examples as well.

I intend to use them for clocking BBD delay-lines for doing karplus strong, which requires a similar frequency range. (200kHz max, according to the datasheet of the MN3006, although they can probably go a bit higher, at least that's what I've heard.)

I did some initial tests and it worked just fine, pretty straight forward actually. There's lots of examples on the net. Shouldn't be to hard to implement using an arduino, especially if you're fine with quantizing to semitones.
if all you need is a square wave vco for downclocking, and want analog, id suggest a 4046 based design. i think the HCT variant is the fastest, around 40MHz. a cmos 555 could also get you close, but its less linear if i recall correctly.
Thanks for that.

I guess something like a version of the TH 4046 VCO, but taking the pin 10 buffered square output and ditching all the tri, saw, sine, pulse, synch, linear FM circuitry.

I guess it just be a matter of using a .1nF rather than a 10n capacitor to change the integration time? (plus similar for the power supply decoupling)

Looking further, I see the famous Sergio Franco's VCO for the SalMar Construction has the right range.

It is in his 1974 PhD. Thesis.
[url=]SalMar Construction Circuit Diagrams[/url]

ASIDE: This is, I think, the origin of the "Franco compensation" for VCOs, i.e a little resistor that compensates for the finite reset time. Where I think Franco gets the engineering right is that he uses a one-shot for this reset, so that he can calculate exactly the value of the compensation resistor R1 (which causes a slightly ahead-of-time trigger of the comparator). Rather than just guessing something in the range for some comparator/diode/transistor arrangement.

(However, he still uses a trimpot for R1 even though he has the formula to calculate an exact value (p33) because the resistor serves double duty of also compensating the bulk resistance (RE) of the LHS (UPDATE: oops I mean RHS) of the exponential conversion pair. )
Ian Fritz's DoubleDeka VCO core runs at over 100kHz I believe, and is claimed to be very stable. I guess the schematics are not public but there's discussion here:
Yes, I tried to find some hints on his circuit. (He designs for key components with fast slew times, he mentions in

Double dekka runs at only about 10x the fundamental frequency (i.e. 1kHz note requires the VCO to clock at 10kHz) , while the ProSolist/Roland/SalMar designs need 64 or 128x, so another order of magnitude) but because they use divide/2 counters for octave selection, the VCOs don't need to have as much accurate range.

I suggest a closed loop VCO. See tes/an14f.pdf
In a closed loop VCO you need no Franco compensation, but maybe a Rossum compensation for your expo

ricko wrote:

(However, he still uses a trimpot for R1 even though he has the formula to calculate an exact value (p33) because the resistor serves double duty of also compensating the bulk resistance (RE) of the LHS of the exponential conversion pair. )

I would rather say " improving the bulk resistance effect". While it is a true (math.correct) compensation for the overshoot time, it's not for RE compansation. A Rossum style compensation is a true compensation for RE, so probably the best compensation would be a fixed (calculated) Franco resistor and a trimmer in the Rossum circuit. Anyway you need an ultrafast comparator with feed forward to trigger the one shot, because there is always a slope (sawtooth/triangle) dependent trigger delay. This is the reason why CMOS-555 designs suck. oops, too off topic now, I shut up
the Tantak Sampler/delay (from the 80's) has a PLL based HF VCO with a stated range of 6 octaves.

I've attached the schematic as I couldn't find a current URL for it.

A couple of key component values (C4,C5) don't appear to be listed, but should be relatively easy to figure out.

EDIT- just taken a second look - the PLL is used a generate a higher 16x frequency to run switched capacitor filters - the HF VCO itself doesn't appear to need ther PLL part of the circuit?
Thanks for that!

The Tanrak VCO is interesting: from what I can make out it is a tri-core where a diode ring is used to select the positive or negative versions of the expo current. I haven't seen that arrangement, I don't think. Complicated diagram, but low parts count with the CA3096.

I wonder if a combination of an 8x audio VCO (conventional but with more attention to a fast comparator) plus an 8x frequency multiplier would avoid a world of problems (that either a 64x VCO or a 64x frequency multiplier might have.)
I've heard CEM3340 can go pretty fast (>1MHz).

You might also take a serious look at the 74HCT9046, a faster and better version of the 4046.
one thing to watch out for in any PLL (or other "control loop") based designs is lock time. its hard to get a small lock time on a wide frequency range PLL. typically you will need a few cycles of the waveform to make a decision and lock, and a few cycles at your lowest frequency might be too long. it does produce interesting audio effects, though, as you quickly play notes of differing frequencies. sort of the vocal "autotune" effect as it tries to lock.
The Real MC
Heterodyning is another technique for high frequency oscillators. It is the core technology for theremins, don't know if it has been attempted for modular synthesis.

For heterodyning, instead of thinking about an accurate VCO in the 1kHz to 100Khz range, I would need to get a circuit for an accurate VCO in the MHz range, yes? Does anyone know of musical circuits for that range? In the back of my mind is the suspicion that requiring even higher frequencies might make the problem harder rather than easier...?
The Real MC wrote:
Heterodyning is another technique for high frequency oscillators. It is the core technology for theremins, don't know if it has been attempted for modular synthesis.
the "steady state fate ultra heterodyne" looks like a VCA, not a VCO. so you could use it to heterodyne two signals, but im not sure that would be easy to do in a musical way. when you multiply two oscillators, you get F1 - F2 (or F1+F2 depending upon which sideband you decide to use), which is no longer a log response, which might be fine for some things, but would make it hard to control with a keyboard.

the jim williams app note linked by elektrouwe is great. the "box section" at the end is a great TL;DR, although its missing the triangle core, which is used in a number of the examples in the paper. this is whats inside the 4046, and a lot of old test equiptment where a diode ring is used (like the tanrak shown above) instead of transistors. you can build something faster than the 4046 using current mode opamps and LTC1043 switch like williams did, but im not sure its necessary. its also worth noting that a lot of examples in the app note are of the "feedback" variety, so although the average number of pulses per unit time will be very accurate, those pulses will dither about, coloring the final output frequency. if its divided down sufficiently you wont notice it, as the divider averages the pulses. again, could be feature and not a bug, depending upon taste.
jorg wrote:
I've heard CEM3340 can go pretty fast (>1MHz).

You might also take a serious look at the 74HCT9046, a faster and better version of the 4046.

Seems like you're right! I just came across the Digisound Voltage Controlled Digital Oscillator, which uses a the 3340 along with some additional circuitry to drive an Eprom containing wavetables.

The manual states a table size of 64 and a frequency range of up to ~10kHz, so that would require a clock frequency of 640kHz. Nice! I have some AS3340s around, so I might give this a try.
ricko VCDO
Looks like they didn't have to change much. Apart from the smaller tuning capacitor and the zener diode/schmitt trigger to dress up the square output, everything around the 3340 looks just like in the datasheet. Or am I missing something? That differentiating frequeny doubler can probably omitted depending on how high you need to go.
Well spotted! I like the idea of that differentiating doubler.

I wonder if some x4 , x6 or x8 would be possible, eg using multiple comparators on the saw out, or an Lm3915? I suppose, when used to clock through addresses, or to derive a signal by logic (like the ARP) as distinct from mixing different divisions like the roland SH3a (& 1000, 2000), small phase error of the highest bits is probably not so important. 5Pulser circuit An LM3914 would bring us closer to IIRC Ian Fritz's 5 Pulser design. (Double Dekka uses an lm331 and 4017 counters.)

(Or a saw doubler, a comparator squarer, and this differentiating dounble to get x4.)

On the topic of frequency multiplication, I see Walton's EM&M graphic oscillator uses a 4046 PLL to get 8x audio in, to match the 8 sliders. rByDGWalton
Trying to figure out the Tanrak VCO speed. Not having entire joy...

Am I right in thinking that while VCO steps through addresses, the successive approximation DAC clocking is independent of the VCO? (And does it just output whenever it has found the approximation, not on a fixed rate?) Is the 31kHz a fixed input sample rate, then?

The text suggests that the VCO operates from 10kHz to 200kHz. So this would fit in with the 6 octave range, from 31k to 31k * 2^6 = 198k.

(But then doubts kick in. Does it really only operate by going faster on playback? In which case, why not have a fixed output filter, not the one that tracks the VZCO x 16? Seems overkill. If it only slows down playback, that would give a linear range of about 500Hz to 31kHz, which is like a 1' or 2' setting on a normal VCO, not exceptional. I guess thus us what simulators are for oops )

(Maybe we get more of a hint about the rough VCO range from the circuit, that the C3 polystrene capacitor is 1000pF? Hmmm. That is not particularly small for an audio rate tricore VCO, is it, looking at other designs. And wouldn't r10 slow down the charge/discharge too?)

(UPDATE: reading another post --cem3340 accuracy-- it seems the sweet range for the 3340 is -4 to +2V. So that would give a nominal freq of 48kHz: that would be the freq produced with 0V input, with a linear range of 6 8ves 3k to 198kHz. The Tanrak does not use the 3340, but is its linear sweet spot pretty similar, since it give about 48k as its nominal frequency?)
ive been thinking about these same issues for a while now, as i wanted to do a lookup table synth with an analog vco, but a lot of my experiments have discouraged me so far. but, this thread renewed my interest, so i built this up:

[EDIT] the capacitor was actually 470pF, not 10pF (grabbed the wrong one while building, but it turned out to be the better value, so i never bothered checking).

it runs from 1kHz to 1MHz, and heres its linearity:

im not sure what the low current linearity error is about, but im guessing some form of charge injection on my protoboard. at higher frequencies, this sort of thing gets worse. i think reducing the signal at the input of the OTA might help here.

also, since it just uses some HC logic for the comparator, there will be temperature drift. an LM311 followed by a logic IC would be more accurate, but slower.
Just a couple of comments.

I agree that triangle-core makes sense for a HFVCO.

4046 and 74HCT9046 are not exactly triangle-core; they do a substantial reset current pulse on the capacitor. Nonetheless, they can run pretty fast.

Frequency-multiplication is definitely prone to phase noise. In RF, there are dedicated PLL chips for that purpose, and they can be clean. They rely on HFVCOs. However, those chips won't work down at the frequencies of interest here. I've built simple doublers for clocking purposes, but they are very sensitive to the source waveform's duty cycle or waveshape (depending on the doubler type). In general, better to build an oscillator that natively runs fast; making one that runs more slowly but cleanly is not any easier than a fast one.

Phase noise, in this application (clocking a BBD or sample playback) is just noise; unfortunately we can't just ignore it.
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