Author 
Quantifying the impact of mismatched transistors? 
cygmu 
Technical question alert.
We know that using matched transistors in a differential pair eliminates the dependence on saturation current, which is itself temperature dependent, so this is good for stability. But, how important is close matching?
It seems to me that using mismatched transistors introduces a multiplication factor of Is1/Is2 , i.e. the ratio of the two saturation currents.
Although the saturation currents individually are extremely temperature dependent (9% per degree K or something), their ratio may not be, particularly if the transistors are reasonably close (but not perfectly matched) in the first place. Using a differential pair, even without matching, is clearly a huge advantage over a single transistor. How much better does it get with matching?
Can we quantify the significance of a mismatch? How does it compare to the effect of V_T which is compensated for in other ways? 

guest 
thats a good question. ive often wondered if 1mV matching is that much better than 500uV matching, for example. i think there are other factors besides for Is, though. the typical model of Is*e^(V/Vt) is an approximation. there is a multiplier next to Vt that is device dependent, and there are leakage currents that add with Is that are device dependent. perhaps a quick spice simulation is in order. 

cygmu 
I haven't really played with Spice  LTSpice doesn't seem to work properly on a Mac so I gave up easily  but I did find material online detailing how Spice models the temperature dependency of Is. I can't find the best one again now but there's an answer on this page:
https://electronics.stackexchange.com/questions/35692/whydoesthebas eemittervoltageofabjtdecreasewithtemperature
This reduces the question to how much variation there is between devices in the various nontemperaturedependent values (I hesitate to say "constants") in that formula, which I definitely do not know! Somewhere I found a page saying that the XTI exponent should be somewhere from 3  3.5. If you are ever motivated to toy with Spice for this then perhaps that is the thing to play with, 

loki 
I would have to go back and do the math to prove it but in the first generation of IC opamps the offset drift was 3micro volts per millivolt of input offset. This is accurate enough to let you estimate the drift contribution of a matched pair. 

cygmu 
Thanks. True story: before posting this, I was discussing with a friend and concluded I didn't know what the answer was, and said "I'll post on MW to see if guest and loki have any insight" ... and here you are
I found some Georgia Tech notes about Vbe mismatch and offset voltage in differential pairs.
https://mghcourses.ece.gatech.edu/ece4430/ECE4430/Unit2/DeviceMismatc h.pdf
In there, it is stated that the variation in Is with temperature can be neglected: the offset temperature dependence is essentially all V_T dependence, if I am understanding properly  I haven't taken it all in. This squares with loki's numbers: V_T varies linearly with temperature, so around room temperature (300K) you will get about 3uV per degree for every 1mV of offset. It seems to me that this is compensated by the tempco arrangement.
Can this be right? I feel like it can't be.
[edited to correct some nonsense about V_T] 

loki 
Do you have a copy of the PDF of the Nonlinear Circuits Handbook from Analog Devices? There is a clear explanation starting on page 10. There are two different and opposite temperature coefficients. The first is compensated by the transistor pair and the second, the scale factor, is compensated by the tempco resistor.
This is a book every synthesizer designer should have:
https://www.analog.com/en/education/educationlibrary/nonlinearcircui tshandbook.html 

cygmu 
Thanks again. I have read that, once upon a time, but will revisit.
Quote: 
There are two different and opposite temperature coefficients. The first is compensated by the transistor pair and the second, the scale factor, is compensated by the tempco resistor.

Exactly. My question is how well a notperfectlymatched pair compensates for the first, I_S derived temperature dependence. The Georgia Tech notes seem to suggest that in a differential pair the temperature dependence of I_S has negligible impact  and those notes are specifically about the case of mismatched pairs.
Of course mismatch introduces an offset voltage in the differential pair. I reckon that a fixed offset voltage is not a problem for an exponential converter. (For a VCA application it would be an issue because of CV feedthrough.) So could it be that for exponential conversion, matching is no big deal? 

loki 
cygmu wrote: 
Of course mismatch introduces an offset voltage in the differential pair. I reckon that a fixed offset voltage is not a problem for an exponential converter. 
But the offset is not fixed, it is changing with temperature. Difference in Vbe is difference in Is. Designing a VCO you should sit down and analyze the sources of error in the circuit and the magnitude of their change with temperature.
There are different levels of accuracy in match. The LM394 was an IC with 50 pairs of transistors connected in parallel with each other. There have been several generations of matched pairs on a single die. Now you can buy pairs that are dice from the same wafer packaged in a SOT363. And there are plenty of people on Muffs who are hand matching discrete transistors.
The hand matched parts will never match the performance of the SOT363 because of the thermal gradient through the packages. In turn the SOT363 will never match the performance of the single die solutions. You have to approach this consciously and decide what level of performance is necessary. And indeed you have, by asking what difference the offset makes.
Graham Hinton keeps pointing out that the specifications on the tempco resistors are so loose that they are a dominant factor in the error budget. 

guest 
i was going to test this, but i cant find 2 transistors in the same package that have a large enough offset voltage. i have some ancient CA3096s, and they are all matched to 0.5mV. worst i can find in my collection is 1mV in an LM3046. i tried 2 seperate transistors, but thats all over the map, and didnt make for a good test. 

cygmu 
loki wrote:  cygmu wrote: 
Of course mismatch introduces an offset voltage in the differential pair. I reckon that a fixed offset voltage is not a problem for an exponential converter. 
But the offset is not fixed, it is changing with temperature.

Yes, sorry  I didn't say that properly. I think it may be that it is mainly scaling with the thermal voltage, i.e. it is fixed as a multiple of V_T.
If the notes from Georgia Tech are to be believed, there are three main temperature dependencies in the offset voltage of a differential pair:
 resistance at the collectors, i.e. external circuitry mismatch, I suppose
 saturation currents of the devices i.e. the device mismatch
 V_T, i.e. the scale factor
It is stated that the temperature dependence of the differences of the first two of these are negligible, leaving you only with the scale factor to worry about. And this is what we attempt to compensate using the tempco arrangement.
These observations point to exactly what you have said: keeping the transistors at the same temperature, and getting the scalefactor temperature compensation correct, are the important points. It seems to me that they may be significantly more important than device matching.
But this is not quite conclusive. It could be the case that the I_S temperature dependencies are negligible only if the devices are tightly enough matched in the first place.
Quote:  And there are plenty of people on Muffs who are hand matching discrete transistors.

Yes, I'm one of them With a little patience for testing multiple parts it is pretty easy to match them more closely than the data sheets of single die matched pairs claim, and the measurements seem to be repeatable so I tend to believe them despite all the evident sources of error in my setup (kids, cats, home heating).
For VCAs I think it is worth continuing to do this, looking for zero offset voltage. For expo converters it seems that measuring the coefficient of your PTC resistor may be more important.
Quote: 
Graham Hinton keeps pointing out that the specifications on the tempco resistors are so loose that they are a dominant factor in the error budget. 
Yes, that's pretty much where my conversations about this started.
I really appreciate your help in thinking this through. Thanks again. 

cygmu 
Reading guest's last post in the context of the rest of this discussion it occurs to me that the whole question may be a moot point. If good thermal coupling is top of the list, then you are restricted to monolithic pairs anyway, and then reasonable matching comes as standard.
I guess some of those SOT363 packages that simply parcel up two transistor dies might be a case to consider, but the "adjacent wafer" ones (which are reasonably well matched) are only a few cents more expensive anyway. 

frijitz 
cygmu wrote:  It seems to me that using mismatched transistors introduces a multiplication factor of Is1/Is2 , i.e. the ratio of the two saturation currents. 
This question came up a "while" ago on the sdiy list, so you might want to dig that up.
My understanding is that the Is ratio may have two different kinds of contributions. Since it is an extensive variable, there can be strictly geometric contributions, specifically Is is proportional to the device area. But intrinsically the leakage current _density_ is a material property.
If the mismatch is just from different areas, then it merely introduces an unimportant constant factor in the Is ratio. If the areas are the same, then mismatch could be due material imperfections that cause leakages with different temperature dependences.
So which is it? I don't think the arguments I've heard really resolved the question. So if anyone knows for sure, please let us know!
An experiment to do would be to take an expo converter with a pretty good V_T tempco and see if unmatched pairs give a lot of extra drift compared to matched ones. I reckon anybody with a good VCO could try this.
Ian 

guest 
the test i plan to run when i find suitable transistors, is keeping Vbe constant on 2 transistors, and measuring their current variations with temperature. this eliminates the need for an accurate tempco. 

cygmu 
I think I found the SDIY archive material that Ian referred to, from 1999.
Rene Schmitz concludes that there is no appreciable temperature effect on the I_s ratio in the differential pair, so that a mismatch results only in a tuning offset, as I began to suspect above. Obviously there is still the V_T scale effect to compensate for. A couple of people agree and nobody disagrees. 

guest 
i feel like the prospect of not needing to matching transistors for a vco is not as advantageous as it once was. you can get pretty well matched pairs for fourteen cents these days. what i was excited about was the ability to use unmatched quads for true vt multiplier schemes, but they dont sell any cheap versions of those anymore (its a buck or two at 100s, and thats if they have them). but, the high precision platinum RTDs are about 1.5$ as well, so maybe worth it? 

cygmu 
guest wrote:  i feel like the prospect of not needing to matching transistors for a vco is not as advantageous as it once was. 
I agree. As I tried to say above, without much clarity (sorry), it seems as though the essentials are the tempco and ensuring that everything is at the same temperature. So you want to use pairs that are in a single package, and among those, decent matching is almost free. It does mean you don't need to hunt for the super matched parts though.
So a single package with good log conformance parts seems to be the thing to shoot for, right? And I seem to recall that you found the dual 3904 transistors to be pretty good in that respect. 

guest 
yeah, the 3904 was suprsingly good. ive been meaning to do another test with some SOT363 3904 parts just to verify (my orignal test used to92). i might pick up a quad as well and see how that goes for a Vt multiplier. 

loki 
cygmu wrote:  So a single package with good log conformance parts seems to be the thing to shoot for, right? And I seem to recall that you found the dual 3904 transistors to be pretty good in that respect. 
Look at the MMDT4401 and the MMDT4403. They are a larger geometry than the 3904 and 3906 and will have lower Rbe. Marshal Leach in discussing phono preamp design talked about using the 2N4401 and 2N4403 as a "secret" ingredient in low noise audio design. 

frijitz 
guest wrote:  the test i plan to run when i find suitable transistors, is keeping Vbe constant on 2 transistors, and measuring their current variations with temperature. this eliminates the need for an accurate tempco. 
I remember trying something like that once with 2N3904’s. You would be looking for a deviation from 3200 ppm/K, right? My results were inconclusive —just too hard to get stable results. That’s why I am suggesting putting in a tempco, to be looking for deviations from a small number. But I would be very interested in hearing your results.
Ian 

frijitz 
cygmu wrote:  I think I found the SDIY archive material that Ian referred to, from 1999.
Rene Schmitz concludes that there is no appreciable temperature effect on the I_s ratio in the differential pair, so that a mismatch results only in a tuning offset, as I began to suspect above. Obviously there is still the V_T scale effect to compensate for. A couple of people agree and nobody disagrees. 
Still, it all seems speculative to me. (You don’t conduct science by voting.) Has anyone but me actually worked on basic semiconductor device R&D?
Ian 

guest 
frijitz wrote:  You would be looking for a deviation from 3200 ppm/K, right? My results were inconclusive —just too hard to get stable results. That’s why I am suggesting putting in a tempco, to be looking for deviations from a small number. 
the idea here, is that both bases are grounded, and the emitters are tied together, with one collector being held at a fixed current via the usual feedback loop. current is then measured on the other collector. in this way, delta Vbe is 0, except for offset voltage varations. and, if offset voltage is linearly proportional to Vt as the georgia tech paper suggets, then the only change in current should be due to unmatched Is variations.
Iout = Iin (Is1/Is2)*e^((deltaVbe + Vos)/Vt) : deltaVbe = 0, Vos~Vt
i tried with 5 different discrete 3904s, and it was all over the place, but i figured that was because the temperatures of the 2 transistors were not the same. 

cygmu 
frijitz wrote: 
Still, it all seems speculative to me. (You don’t conduct science by voting.) Has anyone but me actually worked on basic semiconductor device R&D?

Absolutely agreed. With your help I dug up the textbook on which the Georgia Tech notes must have been based  the exposition is almost identical. It's Gray, Hurst, Lewis and Meyer, "Analysis and Design of Analog Integrated Circuits". In there, the statement is that if the Is ratio variations (and Rc variations) are temperature independent, then the offset voltage will be linear in V_T. On these assumptions they calculate the what offset voltage drift should be and state that "this can be verified by experiment." The required experiment is likely too delicate for my kitchen table though. 

frijitz 
guest wrote:  the idea here, is that both bases are grounded, and the emitters are tied together, with one collector being held at a fixed current via the usual feedback loop. current is then measured on the other collector. in this way, delta Vbe is 0, except for offset voltage varations. 
Not following you. If the emitters are connected together and the bases are connected together, then it seems to me that delta Vbe is zero by definition. There is no Vbe "offset" because you have them pinned together.
I'll try to dig up what I tried before.
Ian 

guest 
i ordered some 3904 quads, so ill try some things out when they arrive.
yes, delta Vbe is zero, as both emitters and bases are tied together. by Vos, i mean the internal mismatch. so even though the emitters and bases are tied together, they will give different collector currents due to this internal "offset voltage", which is really just all of its parameter errors lumped together. if this Vos if proportional to Vt, then i shouldnt see any change in collector currents with temperature. 

cygmu 
guest wrote:  so even though the emitters and bases are tied together, they will give different collector currents due to this internal "offset voltage", which is really just all of its parameter errors lumped together. . 
That should be determined by the Is variation, which appears elsewhere in your equation, and the difference in resistance at the collectors which presumably you are making zero.
For that reason I don't think you need the Vos term in your equation but I do think the experiment should demonstrate how/whether the Is ratio varies with temperature. 

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