A new thru zero triangle core VCO

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devinw1
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A new thru zero triangle core VCO

Post by devinw1 » Tue Oct 29, 2019 10:00 am

I've been recently enamored with the concept of TZ VCOs so I set out on trying to do one that is at least somewhat different from what I've seen that's out there. What I ended up with may seem a bit brute force to some, but it (preliminary) seems to work quite well! The idea is that I use a bunch of JFETs to essentially flip the whole core upside down on a zero crossing.

I have done away with the flip-flop from the EN129 type design and have a single schmitt trigger intead of 2, which is wired up with the JFET switches so that it always toggles, but also flips states upon zero crossing.

I happened to have a huge bag of old 2N5459s that I used to breadboard this, so I'll have to test modern replacements. I think the BF256Bs will work. Also, I think I will try diodes instead of the 1M resistors as well. Not sure which will work better.

My initial schematic is attached. Here is a quick testing to show it indeed does the FM revers-ey thingy:

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Last edited by devinw1 on Wed Oct 30, 2019 1:46 pm, edited 1 time in total.

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Post by guest » Tue Oct 29, 2019 11:40 am

looks good! one quick comment: the dual comparators at the input might not have the exact same comparison voltage due to internal offset differences, so they might not toggle at the same time. using only one comparator, and following it with an inverter would ensure they toggle identically.
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Post by devinw1 » Tue Oct 29, 2019 11:47 am

guest wrote:looks good! one quick comment: the dual comparators at the input might not have the exact same comparison voltage due to internal offset differences, so they might not toggle at the same time. using only one comparator, and following it with an inverter would ensure they toggle identically.
Yeah, good point. I kind of thought of that and was zooming waaay in on my scope while monitoring the output of each on each channel of the scope and the lines seemed to cross right about dead middle, but perhaps luck of the draw on that particular TL072.

The other thing I thought is technically I could use P-channel JFETs for half of the 8 and use have 1 comparator since the Ps will turn off with positive Voltage, but I thought that might create more issues due to the differences in characteristics of the transistors.

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Post by J3RK » Tue Oct 29, 2019 12:04 pm

Nice design! :party:
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Post by DozenCrows » Wed Oct 30, 2019 8:27 am

One thing I don't get from the schematic is how the modulation (MOD) input affects the frequency - it just gets used to switch the core between "forward" and "backward" running.

Is there more to the circuit? Or do you feed the IEXPO signal to MOD, for an exponential TZFM, rather than the "conventional" linear TZFM.

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Post by devinw1 » Wed Oct 30, 2019 10:19 am

DozenCrows wrote:One thing I don't get from the schematic is how the modulation (MOD) input affects the frequency - it just gets used to switch the core between "forward" and "backward" running.

Is there more to the circuit? Or do you feed the IEXPO signal to MOD, for an exponential TZFM, rather than the "conventional" linear TZFM.
Ah yes, I just left that out. :D. You have to use a full wave rectifier on the modulation signal and feed it into the linear FM input on the exponential converter. :tu:

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Post by cygmu » Wed Oct 30, 2019 10:30 am

guest wrote:looks good! one quick comment: the dual comparators at the input might not have the exact same comparison voltage due to internal offset differences, so they might not toggle at the same time. using only one comparator, and following it with an inverter would ensure they toggle identically.
Doesn't the first comparator, that feeds the dual pair, cover that?

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Post by DozenCrows » Wed Oct 30, 2019 10:35 am

devinw1 wrote:Ah yes, I just left that out. :D. You have to use a full wave rectifier on the modulation signal and feed it into the linear FM input on the exponential converter. :tu:
I thought it would be something like that.

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Post by devinw1 » Wed Oct 30, 2019 10:57 am

cygmu wrote:
guest wrote:looks good! one quick comment: the dual comparators at the input might not have the exact same comparison voltage due to internal offset differences, so they might not toggle at the same time. using only one comparator, and following it with an inverter would ensure they toggle identically.
Doesn't the first comparator, that feeds the dual pair, cover that?
The first op amp is a weak schmitt trigger feeding the 2 comparators.

BTW, I tried using an inverter after the first comparator instead of the 2 and it did make the crossings more even. Thanks for that, guest!

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Post by devinw1 » Wed Oct 30, 2019 1:21 pm

An interesting aspect of this circuit (vs. the flip-flop method) I just noticed in slo-mo while running the siumlator is that if the vco core itself is crossing zero at the same time that a FM reversal flip is forced, the reversal does not happen. I'm not sure how this manifests itself in the sound...as it seems to work correctly and doesn't have any odd discontinuties.... This sort of thing makes my brain hurt a little. Actually now that I look at it, I think the flip flop version does the same thing. :hmm: :hihi: :despair:

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Post by guest » Wed Oct 30, 2019 2:14 pm

cygmu wrote:
guest wrote:looks good! one quick comment: the dual comparators at the input might not have the exact same comparison voltage due to internal offset differences, so they might not toggle at the same time. using only one comparator, and following it with an inverter would ensure they toggle identically.
Doesn't the first comparator, that feeds the dual pair, cover that?
yes, thanks for pointing this out. when i first looked at it, i assumed that frist stage was just a CV summing stage, not a schmitt trigger. this means that one of the opamps can be completey removed, as the schmitt trigger output is already the inverted signal that is needed.
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Post by guest » Wed Oct 30, 2019 2:29 pm

devinw1 wrote:An interesting aspect of this circuit (vs. the flip-flop method) I just noticed in slo-mo while running the siumlator is that if the vco core itself is crossing zero at the same time that a FM reversal flip is forced, the reversal does not happen.
is this for an output waveform going +/-5V? for the reversal to not happen, the comparator would have to flip at the same time, basically negating the reversal. i could see this happening up near the transition voltages (+/-5V), but at 0V id figure it would be most stable. the inverting pin wouldnt change at all, and the non inverting pin would go from 1/3Vcc to 1/2Vcc. maybe there is something happening when one switch opens, but the other doesnt close right away. or maybe one switch closes before the other opens, shorting the input every so briefly and causing a flip.
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Post by guest » Wed Oct 30, 2019 2:47 pm

i was thinking that you might be able to get rid of half of the JFETs, as they switch between signal and ground, so the ground path can just be replaced with a resistor which is either driven via the JFET, or floats back down to ground when the JFET is open. so at the OTA input, youd have 2 JFETs, both coming from the signal, one going to the inverting pin, the other to the noninverting. then at each pin there is a 1k resistor to ground. this also eliminates any odd inbetween states if both JFETs are momentarily open during a transistion.

the same can be done with the schmitt trigger opamp, but the resistor values might need to be scaled up a bit to reduce the currrent draw. or, an opamp optional inverter could be put before the schmitt trigger, and then its just one JFET, and none on the schmitt trigger (but an extra opamp).

it might be good to overdrive the OTA a bit, since its just acting as a current switch. right now with the 100k/1k combo, youre getting 100mV drive at the OTA input, which is still within its linear range, so the amount of current that comes out will be a function of temperature and the saturation voltage on the schmitt trigger opamp that drives it. if you decrease the 100k to 20k, its now driven at 500mV, which is well into saturation, and the output will not vary.
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Post by devinw1 » Wed Oct 30, 2019 3:23 pm

guest wrote:i was thinking that you might be able to get rid of half of the JFETs, as they switch between signal and ground, so the ground path can just be replaced with a resistor which is either driven via the JFET, or floats back down to ground when the JFET is open. so at the OTA input, youd have 2 JFETs, both coming from the signal, one going to the inverting pin, the other to the noninverting. then at each pin there is a 1k resistor to ground. this also eliminates any odd inbetween states if both JFETs are momentarily open during a transistion.

the same can be done with the schmitt trigger opamp, but the resistor values might need to be scaled up a bit to reduce the currrent draw. or, an opamp optional inverter could be put before the schmitt trigger, and then its just one JFET, and none on the schmitt trigger (but an extra opamp).

it might be good to overdrive the OTA a bit, since its just acting as a current switch. right now with the 100k/1k combo, youre getting 100mV drive at the OTA input, which is still within its linear range, so the amount of current that comes out will be a function of temperature and the saturation voltage on the schmitt trigger opamp that drives it. if you decrease the 100k to 20k, its now driven at 500mV, which is well into saturation, and the output will not vary.
Very cool.. This morning I realized I could already omit the top right JFET and just wire right to the 5K to ground. All it does is make that resistor end up flowing a little more current when the VCO is in the flipped state (like 1mA ). I just did that and scrapped the other 3 JFETs and wired a 5K to ground at the negative terminal of the schmitt trigger and it all seems to work just as well (on the computer)!

As for the zero crossings, according to simulation it is still missing the flips there. I agree with you guest, it does seem to make sense that it would be more likely to exhibit this near the schmitt trigger points... Not sure whhat is up with that. I'll have to see what it does on the o-scope.

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Post by devinw1 » Wed Oct 30, 2019 3:32 pm

Now that I'm looking at it a little closer, it looks like maybe it is missing doing an inversion only when the following conditions occur:

1) The triangle voltage of the core is above 0 and going from high to low.
2) The modulating signal (into the weak schmitt trigger) is going from high to low. ie. the core's schmitt will be transitioning from an inverting to a non-inverting. :hmm:

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Post by guest » Wed Oct 30, 2019 4:46 pm

is this for the 4 JFET model, or the 8 JFET model? and do you see the schmitt trigger output toggle when this glitch happens? are there any other odd parameters, like really low I_exp?
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Post by devinw1 » Wed Oct 30, 2019 5:12 pm

This is the 4 JFET and also the "JFET controlled inverter before the schmitt" (3 JFET). They seem to behave the same.

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Post by guest » Wed Oct 30, 2019 5:26 pm

since it does the same thing with the JFET controlled inverter, i have no ideas at this point. it will be interesting to hear what it does on the breadboard.
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Post by devinw1 » Wed Oct 30, 2019 5:26 pm

Actually I think I was fooling myself. I think it might be OK. Too much staring at Falstad plots for the day (yeah I know I know... it's not REAL spice!).

What I do see is a little ramp like incontinuity in the schmitt output when the inversion hits near a transition (see attachment). Not sure if that is of much concern or how that manifests in reality though.

I'll breadboard up the new version(s) tonight. :tu:
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Post by guest » Wed Oct 30, 2019 5:46 pm

i think that might be a glitch at the transition voltage. it should be inverting, but its not, because the flip flop comparison voltage moved at the exact same time it crossed the threshold. its the main failure mode of this TZVCO topology. its next to impossible to eliminate, so its best to ensure the circuit is tolerant to the failure (it doesnt lock-up).
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Post by devinw1 » Wed Oct 30, 2019 11:20 pm

Well, I built up the 4 transistor version tonight and it worked out quite well! I had to put a 500R trimmer in before the JFET on the + terminal of the schmitt in order to balance out the triangle wave Peak-Peak (and thus slight pitch difference between + and - modes of the VCO). This did the trick. Guessing the difference is because of the difference in RdsOn of the 2 transistors? The simulation said I could switch in higher values for the 10K dangling from the schmitt - but this did not help in reality, even up to 5M. My latest schematic is attached.

Here's a video of some slightly out of tune waves doing inversions driven by the other wave:



It all works quite well and smooth and when I put the FM part back in the circuit I got some lovely TZ modulations. :sb: :sb: :sb:

guest, when you say "lock up" as a failure mode, do you mean failing to flip completely or just stopping the Vco from oscillating ? Or is it more subtle than that?

Thanks for all the input on this btw. Always appreciated! :guinness:
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Post by guest » Thu Oct 31, 2019 12:42 am

thats looking good.

so the frequency changes because the amplitude changes between positive and negative input CVs? i think there are a few things at play here. first, the thresholds change between the 2 configuration. lets say we have some +/-Vo at the output of the opamp. for the noninverting configuration the thresholds are +/-10Vo/24, and for the inverting configuration they are +/-20Vo/44, so close, but not the same. if you change the 24k to 20k, they would match.

the next thing to consider is the effect of Rds,on. lets assume an Rds,on of 200ohms, and lets call the comparison threshold Vc. for the inverting case the input signal would need to be 0.2Vc/10 larger than Vc, due to the attenuation of Rds,on. for the noninverting case, the current has to flow through two 10k resistors, so you get double the voltage drop, or an increase of 0.4Vc/10 at the triangle wave. so increasing the resistor at the inverting pin to 20k would help here.

switching to larger value resistors might help, as it reduces the effect of Rds,on. of course, this will also increase the transition time between states, as those R values will couple with stray capacitance. lets say you have 10pF of stray capacitance (that would be a very high value) and 100k resistors. thats 100k*10pF = 1us time constants, which is not great.
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Post by guest » Thu Oct 31, 2019 1:03 am

ill have to give some thought to the lock up issue. i know i was seeing it on a similar circuit a while back, but i cant convince myself that its a systemic failure.
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Post by devinw1 » Thu Oct 31, 2019 10:39 am

guest wrote:thats looking good.

so the frequency changes because the amplitude changes between positive and negative input CVs?
Yeah exactly. I had gone with a 24k to get more or less 10Vpp on the triangle, but then I noticed when switching reversals using a really slow LFO, the triangle would bump between 9.8Vpp and 10.4Vpp and have a slight pitch difference. IMO, the pitch difference wouldn't really matter, as this would only occur during Frequency Modulation anyway, but I like the idea of the wave staying exactly constant during FM - which fixes the pitch shift anyway.

Totally makes sense about the schmitt thresholds though! If my math is correct, I should be able to maintain 10Vpp nominal and change the resistor on the + terminal to ground from 10k to 7.14k. Or perhaps (in real world terms) I put a 6.8k standard in series with a 1k trimpot wired as a rheostat in there..

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Post by J3RK » Thu Oct 31, 2019 10:50 am

I love the simplicity of this core for getting TZ functionality. (as opposed to a bunch of logic ICs anyway) You can also get a nearly "free" sine shaper with the second half of the OTA IC.

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