CLK2A / Dual Divide midi reset question

[adam s]

I posted a generalized version of this question here: viewtopic.php?f=4&t=241872

I'm trying to get my head around something. My goal is to be able to start/stop/start my midi sequencer (Elektron Machinedrum) and have the clock dividers reset to the start of the beat. I'm using a CV.OCD to get 16th note triggers and the transport play trigger. When I press play, the play event and the first 16th note of the beat happen at logically the same time, but physically one must come ever so slightly after the other (probably sub-1ms). As a result, the clock divider advances and all my subsequent divided gate outputs are a 1/16th note early. Is this the expected result?

It would be awesome if a clock divider would register the reset signal and enact the reset on the subsequent clock tick. It would be necessary for resets to happen before clock, e.g. on transport stop. Better, a reset coming immediately after a clock tick (within some small time window) could just reset the divider as it currently does. So in other words: the logic would go

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if ((reset_time - last_clock_time) > 0 && (reset_time - last_clock_time) < 1ms)
	immediate_reset()
else
	deferred_reset()

Indeed, I've tried a workaround of delaying the reset with the DDSR, which works but it a pretty elaborate hack that I won't do in practice. Actually, the best workaround I've found is to invert the divided signal, which I think works because the duty cycle of the divided pulses lines up to a 16th note (not sure what sorcery accounts for that!).

[BugBrand]

Sorry for the slow reply.
I think I get what you're saying though always get my head in a twist trying to think of how this 'should' be - also considering the designs are always based on 4000 series CMOS chips, not 'clever' microprocessors. (Basically I am basic!)
Is there a way to use the CV.OCD to send a reset pulse delayed as you describe?

[adam s]

My brain obviously went to an overly fancy solution, when I finally realized it is quite simple (actually Jason of Sixty Four Pixels spoon fed me this). I can just invert the reset signal, so the rising edge happens at the end of that pulse rather than at the beginning, ensuring that the reset happens ever so slightly after the clock tick. Here's a pretty bad illustration of how this solves the problem.

before: reset counts clock tick #1, and the clock input immediately advances to click tick #2

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count ___12______3______4______5______6______7______8______
clock ____---____---____---____---____---____---____---____
reset ___---_______________________________________________

after: first clock input counts from wherever the divider was, then inverted reset rising edge of reset signal counts from 1

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count ____?_1____2______3______4______5______6______7_____
clock ____---____---____---____---____---____---____---____
reset ---___-----------------------------------------------

Lucky for me, I have a Triple Logic Gates right next to my CLK2A, so I have a NOT gate handy to do this

[BugBrand]

Glad there are people smarterer than me to make such suggestions!